probably done?

A5/main.c

@@ -159,8 +159,6 @@ int main(int argc, char* argv[]) {
         bool is_store = (is_mem_access &&  pick_one(3,minor_op));
         bool is_conditional = (is_cflow || is_imm_cbranch) && !(is(0xE, minor_op) || is(0xF, minor_op));
 
-        // TODO 2021: Add additional control signals you may need below....
-
         // setting up operand fetch and register read and write for the datapath:
         bool use_imm = is_imm_movq | is_imm_arithmetic | is_imm_cbranch;
         val reg_read_dz = or(use_if(!is_leaq, reg_d), use_if(is_leaq, reg_z));
@@ -231,7 +229,7 @@ int main(int argc, char* argv[]) {
 
         // determine the next position of the program counter
         bool is_jump = is_cflow && (is(0xF,minor_op) || (is_conditional && !reduce_or(compute_result)));
-        val pc_next_if_not_control = use_if(!is_jump, pc_incremented);
+        val pc_next_if_not_control = use_if(!(is_jump || is_return), pc_incremented);
         val pc_next_if_jump = use_if(is_jump, target);
         val pc_next_if_return = use_if(is_return, reg_out_b);
         val pc_next = add(add(pc_next_if_not_control, pc_next_if_jump), pc_next_if_return);
@@ -242,7 +240,6 @@ int main(int argc, char* argv[]) {
 
         /*** WRITE ***/
         // choose result to write back to register
-        // TODO 2021: Add any additional results which need to be muxed in for writing to the destination register
         bool use_compute_result = !is_load && (use_agen || use_multiplier || use_shifter || use_direct || use_alu);
         val datapath_result = or(use_if(use_compute_result, compute_result),
                                  use_if(is_load, mem_out));
@@ -251,7 +248,6 @@ int main(int argc, char* argv[]) {
         reg_write(regs, reg_d, datapath_result, reg_wr_enable);
 
         // write to memory if needed
-        printf("%i\n",is_store);
         memory_write(mem, agen_result, reg_out_a, is_store);
 
         // update program counter