NikolajDanger/Compsys-2021-Assignments
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Nikolaj
2021-12-16 16:49:38 +01:00
parent 281b65339c
commit 19ea6644e4
13 changed files with 289 additions and 7 deletions
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34
A5/main.c
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@@ -105,6 +105,7 @@ int main(int argc, char* argv[]) {
val reg_s = pick_bits(0, 4, inst_bytes[1]);
val reg_z = pick_bits(4, 4, inst_bytes[2]);
val shamt = pick_bits(0, 4, inst_bytes[2]);
val target = pick_bits(0, 8, inst_bytes[2]);
// decode instruction type from major operation code
bool is_return_or_stop = is(RETURN_STOP, major_op);
@@ -122,9 +123,24 @@ int main(int argc, char* argv[]) {
bool is_imm_cbranch = is(IMM_CBRANCH, major_op);
// Right now, we can only execute instructions with a size of 2.
// TODO 2021:
// from info above determine the instruction size
val ins_size = from_int(2);
bool size_is_2 = (is_return_or_stop || is_reg_arithmetic || is_reg_movq || is_reg_movq_mem || is_leaq2);
val size_2 = use_if(size_is_2, from_int(2));
bool size_is_3 = (is_leaq3);
val size_3 = use_if(size_is_3, from_int(3));
bool size_is_6 = (is_cflow || is_imm_arithmetic || is_imm_movq || is_imm_movq_mem || is_leaq6);
val size_6 = use_if(size_is_6, from_int(6));
bool size_is_7 = (is_leaq7);
val size_7 = use_if(size_is_7, from_int(7));
bool size_is_10 = (is_imm_cbranch);
val size_10 = use_if(size_is_10, from_int(10));
val add_1 = add(size_2, size_3);
val add_2 = add(add_1, size_6);
val add_3 = add(add_2, size_7);
val add_4 = add(add_3, size_10);
val ins_size = add_4;
// broad categorization of the instruction
bool is_leaq = is_leaq2 || is_leaq3 || is_leaq6 || is_leaq7;
@@ -139,9 +155,9 @@ int main(int argc, char* argv[]) {
bool imm_p_pos6 = is_imm_cbranch; /* all other at position 2 */
// unimplemented control signals:
bool is_load = false; // TODO 2021: Detect when we're executing a load
bool is_store = false; // TODO 2021: Detect when we're executing a store
bool is_conditional = false; // TODO 2021: Detect if we are executing a conditional flow change
bool is_load = (is_mem_access && !pick_one(3,minor_op));
bool is_store = (is_mem_access && pick_one(3,minor_op));
bool is_conditional = (is_cflow || is_imm_cbranch) && !(is(0xE, minor_op) || is(0xF, minor_op));
// TODO 2021: Add additional control signals you may need below....
@@ -214,8 +230,11 @@ int main(int argc, char* argv[]) {
val pc_incremented = add(pc, ins_size);
// determine the next position of the program counter
// TODO 2021: Add any additional sources for the next PC (for call, ret, jmp and conditional branch)
val pc_next = pc_incremented;
bool is_jump = is_cflow && (is(0xF,minor_op) || (is_conditional && !reduce_or(compute_result)));
val pc_next_if_not_control = use_if(!is_jump, pc_incremented);
val pc_next_if_jump = use_if(is_jump, target);
val pc_next_if_return = use_if(is_return, reg_out_b);
val pc_next = add(add(pc_next_if_not_control, pc_next_if_jump), pc_next_if_return);
/*** MEMORY ***/
// read from memory if needed
@@ -232,6 +251,7 @@ int main(int argc, char* argv[]) {
reg_write(regs, reg_d, datapath_result, reg_wr_enable);
// write to memory if needed
printf("%i\n",is_store);
memory_write(mem, agen_result, reg_out_a, is_store);
// update program counter